Silicon Nanowire FinFETs

Some of the fundamental problems of ultra-small MOSFETs beyond sub-10nm channel length are the electrostatic limits, source-to-drain tunnelling, carrier mobility degradation, process variations, and static leakage. The trend toward ultra-short gate length MOSFETs re‐ quires a more and more effective control of the channel by the gate leading to new device architecture. It appears that non-classical device architectures can extend the CMOS lifetime and provide solutions to continue scaling. In case of silicon-based CMOS technologies, pla‐ nar MOSFETs are limited to scaling beyond 15 nm technology node. As simple scaling of silicon CMOS becomes increasingly complex and expensive, there is considerable interest in increasing performance by using strained channels which can improve carrier mobility and drive current in a device. Multi-gate MOSFETs based on the concept of volume inversion are widely recognized as one of the most promising solutions for meeting the ITRS roadmap requirements. A wide variety of multi-gate architectures, including Double-Gate (DG), GateAll-Around (GAA), Pi-FET and Fin Field-Effect Transistors (FinFETs), rectangular or cylin‐ drical nanowire MOSFETs has been proposed in the literature. In all cases, these structures exhibit a superior control of short channel effects resulting from an exceptional electrostatic coupling between the conduction channel and the surrounding gate electrode. The nanowire (NW) transistors can be seen as the ultimate integration of the innovative nanodevices and is one of the candidates which have gained significant attention from both the device and cir‐ cuit developers because of its potential for building highly dense and high performance electronic circuits. Recent advances in nanoscale fabrication techniques have shown that semiconductor nanowires may become the candidate for next generation technologies. Si and Ge nanowire transistors are also important because of their compatibility with the CMOS technology.